1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same and, more specifically, to a semiconductor device and a method for fabricating the same which can prevent dielectric breakdown of the gate insulation film while allowing micronization of the wiring.
2. Description of the Related Art
Recently micronization of semiconductor devices, as of LSI, etc., has been advanced, and the gate insulation films of field-effect transistors tend to be accordingly thinned.
Thin gate insulation films are vulnerable to electric stresses. The gate insulation films have dielectric breakdown when the gate insulation films are subjected to strong electric stresses.
A factor for causing dielectric breakdown of a gate insulation film has been conventionally considered to be mainly that a high electric stress is applied to the gate insulation film due to inhomogeneity of a plasma for patterning the gate electrode.
However, it has been found that even in a case that the inhomogeneity of a plasma for patterning the gate insulation film is corrected, dielectric breakdown tends to take place in the gate insulation film in fabricating a semiconductor device having a micronized wiring gap.
A semiconductor device fabrication method which causes dielectric breakdown in a gate insulation film will be explained with reference to FIGS. 8A to 8D. FIGS. 8A to 8D are sectional views of a conventional semiconductor device in the steps of the method for fabricating the same, which explain the fabrication method.
As shown in FIG. 8A, first a device isolation film 116 is formed on a semiconductor substrate 110. Then, a gate insulation film 124 is formed in device regions defined by the device isolation film 116. Next, gate electrodes 126 are formed on the gate insulation film 124. A source/drain diffused layer (not shown) is formed by self-alignment with the gate electrodes 126, and transistors 128 each having the gate electrodes 126 and the source/drain diffused layer are formed.
Next, an inter-layer insulation film 130 is formed on the entire surface, and contact holes 132 which arrive at the gate electrodes 126 are formed. Then, a wiring material film 144 is formed. Next, a photoresist mask 146 for forming a wiring is formed on the wiring material film 144.
Then, the wiring material layer 144 is etched with the photoresist mask 146 as a mask. In this etching, although no special problem takes place in a semiconductor device having a large pattern gap, the microloading effect that an etching rate is decreased in regions having a smaller pattern gap takes place in a micronized semiconductor device having a smaller pattern gap. At this time, positive electrons are accelerated by a sheath electric field on the substrate surface to be incident substantially vertically to the semiconductor substrate 110, while electrons are decelerated by the sheath electric field to be incident at an angle to the semiconductor substrate 110. Accordingly, in regions where the photoresist mask 146 has a smaller pattern gap, more electrons are incident on the side surfaces of the photoresist mask 146, and more positive electrons are incident on the wiring material film 144 (see FIG. 8B).
As the etching advances, the photoresist mask 146, on which more electrons have been incident, is charged negative, and the wiring material film 144, on which more positive electrons have been incident, is charged positive. Thus, a positive charge is charged up in the wiring material film 144 and the gate electrodes 126.
The charge-up advances, and when a voltage which exceeds a voltage resistance of the gate insulation film 124 between the semiconductor substrate 110 and the gate electrodes 126, dielectric breakdown takes place in the gate insulation film 124 to discharge the positive electric charge to the side of the semiconductor substrate 110 (see FIG. 8C).
Then, in order to prevent such charge-up damage, a technique in which protection diodes are inserted between the gate electrodes 126 and the semiconductor substrate 110 is proposed. The insertion of the protection diodes between the gate electrodes 126 and the semiconductor substrate 110 can make small a potential difference between the gate electrodes 126 and the semiconductor substrate 110. The occurrence of the dielectric breakdown in the gate insulation film 124 can be thus precluded.
However, it is difficult to connect all the gate electrodes to the protection diodes, thereby hindering higher integration of the semiconductor device.
From the viewpoint that the charge-up damage tends to take place in wirings having higher antenna ratios, which are values given by dividing a wiring area by a gate area, it is considered that the protection diodes are connected only to wirings having higher antenna ratios. However, it is not easy to determine those of the gate electrodes to be connected to the protection diodes, based on antenna ratios computed from design data, etc.
An object of the present invention is to provide a semiconductor device and a method for fabricating the same which can prevent dielectric breakdown of the gate insulation film.
The above-described object is achieved by a semiconductor device comprising: a first transistor including a first gate electrode formed on a substrate through a first gate insulation film; a first insulation film formed on the first transistor and the substrate; a plurality of first wirings formed on the first insulation film, spaced from each other by a first gap; and a second wiring formed on the first insulation film, spaced from either of the first wirings by a second gap which is substantially equal to the first gap, either of the first wirings being electrically connected to the first gate electrode, the second wiring being electrically connected to the substrate. The second wiring is formed on the first insulation film, spaced from the first wiring by a gap which is substantially equal to a first gap, whereby the first wirings and the second wiring can be kept connected up to a certain timing. Furthermore, the second wiring is connected to the substrate, and the first wiring is connected to the first gate electrode of the first transistor, whereby even when the first wiring and the second wiring are charged up with an electric charge, an electric field applied to the first gate insulation film can be small, and dielectric breakdown of the first gate insulation film can be precluded.
The above-described object is achieved by a method for fabricating the semiconductor device comprising the steps of: forming a transistor including a gate electrode formed through a gate insulation film on a substrate; forming an insulation film on the substrate and the transistor; forming a wiring material film on the insulation film; and etching the wiring material film to form first wirings at least either of which is electrically connected to the gate electrode, and a second wiring electrically connected to the substrate, in the step of etching the wiring material film, the second wiring being formed, spaced from either of the first wirings by a second gap which is substantially equal to a first gap by which the first wirings are spaced from each other. The second wiring is formed on the first insulation film, spaced from the first wiring by a gap which is substantially equal to a first gap, whereby the first wirings and the second wiring can be kept connected up to a certain timing. Furthermore, the second wiring is connected to the substrate, and the first wiring is connected to the gate electrode, whereby even when the first wiring and the second wiring are charged up with an electric charge, an electric field applied to the gate electrode can be small, and dielectric breakdown of the gate insulation film can be precluded.
The above-described object is achieved by a method for fabricating the semiconductor device comprising the steps of: forming a transistor including a gate electrode formed through a gate insulation film on a substrate; forming an insulation film on the substrate and the transistor; forming a first conductor plug buried in the insulation film electrically connected to the gate electrode, and a second conductor plug buried in the insulation film electrically connected to the substrate; forming a wiring material film on the first conductor plug, the second conductor plug and the insulation film; and etching the wiring material film to form a first wiring connected to the first conductor plug, and a second wiring connected to the second conductor plug, in the step of etching the wiring material film, the wiring material film being etched in state where the first conductor plug and the second conductor plug are electrically connected to each other through the wiring material film.
As described above, according to the present invention, because the dummy wiring is formed, spaced from the wiring by a gap which is substantially equal to a gap between the wiring and its adjacent one, the wirings and the dummy wiring can be kept connected to each other up to a certain timing. Furthermore, a part of the wiring material film corresponding to the dummy wiring is connected to the substrate, and a part of the wiring material film corresponding to the wirings are connected to the gate electrodes of the transistors, whereby even when the wiring material film is charged up with a positive electric charge, an electric field applied to the gate insulation film can be small, and dielectric breakdown of the gate insulation film can be prevented.
In addition, according to the present invention, dielectric breakdown of the gate insulation film of the transistors can be precluded not only when a first layer wiring is formed, but also when a second layer wiring is formed.
Furthermore, according to the present invention, dielectric breakdown of the gate insulation film of the transistors can be prevented not only when the second layer wiring is formed, but also when a third layer wiring is formed.